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E2E1033 -27-Y6 Semiconductor
Semiconductor MSM66585/586/587/P587/Q587
Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit Microcontroller
el im This version: Jan. 1998 MSM66585/586/587/P587/Q587 ina ry Previous version: Nov. 1996
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GENERAL DESCRIPTION
MSM66585/586/587 are high-performance CMOS 16-bit microcontrollers that integrate a 16bit CPU, ROM, RAM, 8-bit A/D converter, serial port, timers, and PWM. They also allow ROM and RAM to be expanded externally. The MSM66P587 is of OTP (One-Time PROM) version and the MSM66Q587 is of Flash EEPROM version.
FEATURES
* Powerful instruction set Instruction set superior in orthogonal matrics 8/16-bit arithmetic instructions Multiply/divide instructions Bit manipulation instructions Bit logical operation instructions ROM table reference instructions * Abandant addressing modes Register addressing Page addressing Pointer register indirect addressing Stack addressing Immediate addressing * Minimum instruction cycle 100 ns at 20 MHz (4.5V-5.5V) 200 ns at 10 MHz (2.7V-5.5V) * Program memory (ROM) Internal: 64 KB (M66587/M66P587/M66Q587), 48 KB (M66585/586) External: 1 MB, EA pin active * Data memory (RAM) Internal: 2 KB External: 1022 KB * I/O ports Analog input-only port: 4 lines (test pins for M66585) Input/output port: Maximum 80 lines (40 lines with programmable pull-up) * Timers Free-running counter: 16-bit 1 Realtime output: 16-bit 2 General autoreload timer: 8-bit 1 * 16-bit PWM Input clock divider: 1 divider * 8-bit serial port Synchronous with BRG: 1 port
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Semiconductor
MSM66585/586/587/P587/Q587
* A/D converter 8-bit resolution: 4 channels * Interrupts Non-maskable: 1 interrupt Maskable: 9 internal, 4 external (12 vectors) 3-level priority * ROM window function * Standby modes Halt mode Stop mode * Package 100-pin TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM66585TS-K) (Product name : MSM66586TS-K) (Product name : MSM66587TS-K) (Product name : MSM66P587TS-K) (Product name : MSM66Q587TS-K)
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BLOCK DIAGRAM
*1. 48KB for M66585 and M66586. *2. M66585 has no internal A/D converter.
Semiconductor
P2_4/RT08 P2_5/RTO9
16-bit RTO/PWM Timer
CPU Core Control Registers SSP LRB PSW PC Memory Control Pointing R Local R. RAM 2 KB
EA ALE/P5_5 PSEN/P5_4 RD/P7_1 WR/P7_0 WAIT/P7_2 AD0/P0_0 AD7/P0_7 A8/P1_0 A15/P1_7 A16/P9_0
Bus Port Control
DSR TSR CSR
P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P7_4/PWM0 VREF AGND AI0 AI3 P4_0/ETMCK P6_0/INTO P6_1/INT1 P12_2/INT2 P12_3/INT3 NMI P7_3/CLKOUT Event Timer Serial Port ALU PWM *2 A to D Converter ALU Control ACC
ROM 64 KB
*1
Instruction Decoder
A19/P9_3
MSM66585/586/587/P587/Q587
System Control Interrupt
Port Control
OSC0
RES OSC1
P12 P10 P9 P8 P7 P6 P5 P4 P2 P1 P0
Peripheral
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Semiconductor
MSM66585/586/587/P587/Q587
PIN CONFIGURATION (TOP VIEW)
97 P6_2/RXD1 99 P6_4/RXC1 98 P6_3/TXD1 82 P2_5/RT09 100 P6_5/TXC1 81 P2_4/RT08 96 P6_1/INT1 95 P6_0/INT0
92 P10_7
91 P10_6
90 P10_5
89 P10_4
88 P10_3
87 P10_2
86 P10_1
85 P10_0
84 P2_7
83 P2_6
80 P2_3
79 P2_2
78 P2_1
77 P2_0
12_0 P12_1 INT2/P12_2 INT3/P12_3 P12_4 P12_5 P12_6 P12_7 VDD
1 2 3 4 5 6 7 8 9
76 P9_7 75 P9_6 74 P9_5 73 P9_4 72 P9_3/A19 71 P9_2/A18 70 P9_1/A17 69 P9_0/A16 68 GND 67 VDD 66 P1_7/A15 65 P1_6/A14 64 P1_5/A13 63 P1_4/A12 62 P1_3/A11 61 P1_2/A10 60 P1_1/A9 59 P1_0/A8 58 P0_7/AD7 57 P0_6/AD6 56 P0_5/AD5 55 P0_4/AD4 54 P0_3/AD3 53 P0_2/AD2 52 P0_1/AD1 51 P0_0/AD0 ALE/P5_5 50
94 GND 32
*(VDD) VREF 10 (GND) AGND 11 (TEST0) AI0 12 (TEST1) AI1 13 (TEST2) AI2 14 (TEST3) AI3 15 GND 16 VDD 17 ETMCK/P4_0 18 P4_1 19 P4_2 20 P4_3 21 P4_4 22 P4_5 23 P4_6 24 P4_7 25 28 29 30 31 33 34 35 36 VDD 37 38 39 40 41 42 43 44 45 46 47 RD/P7_1 48 WR/P7_0 P5_4PSEN/P5_4 49 P8_1 27 26
P8_0
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
93 VDD
RES
NMI
EA
CLKOUT/P7_3
PWM0/P7_4
*
For MSM66585, pin name is in parentheses ( ).
WAIT/P7_2
OSC0
OSC1
P7_7
P7_6
P7_5
GND
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Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS
Symbol Type Description Port 0 is 8 input/output pins. Input or output can be specified for each bit with the Port 0 Mode Register (P0IO). Pull-up resistors can be specified for each bit with the Port 0 Pull-Up Register (P0PUP). These pins also function as time-multiplexed address outputs and data input/output pins (AD0-AD7) when accessing memory that has been expanded externally (program or data memory). After reset (by RES signal input, BRK instruction execution, or op code trap), P0 will be high-impedance inputs. Port 1 is 8 input/output pins. Input or output can be specified for each bit with the Port 1 Mode Register (P1IO). Pull-up resistors can be specified for each bit with the Port 1 Pull-Up Register (P1PUP). P1_0-P1_7 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 1 Secondary Function Control Register (P1SF). The input/output settings by P1IO will be ignored for pins that have been set to the secondary function by P1SF. These pins function as output pins for address A8-A15 when accessing program memory or data memory that has been expanded externally. When the EA pin is low, A8-A15 will be output regardless of P1SF settings. After reset (by RES signal input, BRK instruction execution, or op code trap), P1 will be high-impedance inputs. P2_4 and P2_5 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 2 Secondary Function Control Register (P2SF). The input/output settings of P2IO will be ignored for pins that have been set to the secondary function by P2SF. These pins output a previously set level when the value of Timer Registers 8 and 9 match a selected counter value. After reset (by RES signal input, BRK instruction execution, or op code trap), P2 will be high-impedance inputs. Port 4 is 8 input/output pins. Input or output can be specified for each bit with the Port 4 Mode Register (P4IO). Pull-up resistors can be specified for each bit with the Port 4 Pull-Up Register (P4PUP). P4_0 also has a secondary function as an input pin for internal operation. Its secondary function can be set for the bit with the Port 4 Secondary Function Control Register (P4SF). The input/output settings by P4IO will be ignored for pins that have been set to the secondary function by P4SF. This is the external clock input pin for the counter of a general 8-bit timer. After reset (by RES signal input, BRK instruction execution, or op code trap), P4 will be high-impedance inputs. Port 5 is 2 input/output pins. Input or output can be specified for each bit with the Port 5 Mode Register (P5IO). P5_4 and P5_5 also have a secondary function as output pins for internal operation. Their secondary function can be set for each bit with the Port 5 Secondary Function Control Register (P5SF). The input/output settings of P5IO will be ignored for pins that have been set to the secondary function by P5SF. PSEN (P5_4): This pin outputs the strobe signal for read operations when external program memory is accessed. Operation will automatically switch to the secondary function when the EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low. ALE (P5_5): This pin outputs the strobe for externally latching the lower 8 address bits output from P0 when external memory is accessed. Operation will automatically switch to the secondary function when the EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low. After reset (by RES signal input, BRK instruction execution, or op code trap), P5 will be high-impedance inputs.
P0_0-P0_7/ AD0-AD7
I/O
P1_0-P1_7/ A8-A15
I/O
P2_0-P2_3 P2_4-P2_5/ RT08-RT09 P2_6-P2_7 I/O
P4_0/ETMCK P4_1-P4_7
I/O
P5_4/PSEN P5_5/ALE
I/O
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Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol Type Description Port 6 is 6 input/output pins. Input or output can be specified for each bit with the Port 6 Mode Register (P6IO). P6_0-P6_5 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 6 Secondary Function Control Register (P6SF). The input/output settings of P6IO will be ignored for pins that have been set to the secondary function by P6SF. INT0 (P5_0), INT1 (P6_1): These pins input external interrupts 0 and 1. RXD1 (P6_2): This pin inputs receive data to the Serial Port 1 receive circuit. TXD1 (P6_3): This pin outputs transmit data to the Serial Port 1 transmit circuit. RXC1 (P6_4): This pin outputs the shift clock when the Serial Port 1 receive circuit is in master mode. It inputs the shift clock when the receive circuit is in slave mode. TXC1 (P6_4): This pin outputs the shift clock when the Serial Port 1 transmit circuit is in master mode. It inputs the shift clock when the transmit circuit is in slave mode. After reset (by RES signal input, BRK instruction execution, or op code trap), P6 will be high-impedance inputs. Port 7 is 8 input/output pins. Input or output can be specified for each bit with the Port 7 Mode Register (P7IO). P7_0-P7_4 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 7 Secondary Function Control Register (P7SF). The input/output settings of P7IO will be ignored for pins that have been set to the secondary function by P7SF. WR (P7_0): This pin outputs the strobe signal for write operations when external data memory is accessed. RD (P7_1): This pin outputs the strobe signal for read operations when external data memory is accessed. WAIT (P7_2): This pin inputs a wait to the internal CPU when external data memory with a slow access time is accessed. CPU is driven to "WAIT" state during WAIT pin high. CLKOUT (P7_3): This pin outputs the clock pulses set by the Peripheral Control Register (PRPHF). PWM0 (P7_4): This pin outputs PWM0. After reset (by RES signal input, BRK instruction execution, or op code trap), P7 will be high-impedance inputs. When P7_0 and P7_1 are used as their secondary functions (WR, RD), they need to be connected externally to pull-up resistors. Port 8 is 8 input/output pins. Input or output can be specified for each bit with the Port 8 Mode Register (P8IO). After reset (by RES signal input, BRK instruction execution, or op code trap), P8 will be high-impedance inputs.
P6_0/INT0 P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1
I/O
P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4/PWM0 P7_5-P7_7
I/O
P8_0-P8_7
I/O
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Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS (Continued)
Symbol Type Description Port 9 is 8 input/output pins. Input or output can be specified for each bit with the Port 9 Mode Register (P9IO). Pull-up resistors can be specified for each bit with the Port 9 Pull-Up Register (P9PUP). P9_0-P9_3 also have a secondary function as output pins for internal operation. Their secondary function can be set for each bit with the Port 9 Secondary Function Control Register (P9SF). The input/output settings of P9IO will be ignored for pins that have been set to the secondary function by P9SF. A16-A19 (P9_0-P9_3): These pins function as output pins for address A16-A19 when accessing program memory or data memory that has been expanded externally. Note that program memory address A16-A19 will be output even when accessing data memory that has been expanded externally. When the EA pin is low and program memory that has been expanded externally is accessed, A16-A19 will be output regardless of P9SF settings. After reset (by RES signal input, BRK instruction execution, or op code trap), P9 will be high-impedance inputs. Port 10 is 8 input/output pins. Input or output can be specified for each bit with the Port 10 Mode Register (P10IO). Pull-up resistors can be specified for each bit with the Port 10 Pull-Up Register (P10PUP). After reset (by RES signal input, BRK instruction execution, or op code trap), P10 will be high-impedance inputs. Port 12 is 8 input/output pins. Input or output can be specified for each bit with the Port 12 Mode Register (P12IO). P12_2 and P12_3 also have a secondary function as input pins for internal operation. Their secondary function can be set for each bit with the Port 12 Secondary Function Control Register (P12SF). The input/output settings of P12IO will be ignored for pins that have been set to the secondary function by P12SF. INT2 (P12_2), INT3 (P12_3): These pins input external interrupts 2 and 3. After reset (by RES signal input, BRK instruction execution, or op code trap), P12 will be high-impedance inputs. These are analog input pins for the A/D converter (test pins for MSM66585). This is the reference voltage pin for the A/D converter (VDD for MSM66585). This is the ground input pin for the A/D converter (GND for MSM66585). This pins connect to a crystal oscillator, ceramic oscillator, or capacitors for base clock oscillation. When the base clock is to be supplied externally, it should be input on the OSC0 pin with the OSC1 pin left open. This input pin requests a non-maskable interrupt. This is an active-low reset input pin. When this pin is high, program addresses 0H-FFFFH will access internal program memory and program addresses 10000H-FFFFFH will access external program memory. To access external program memory, P1, P5, and P9 must be set with their secondary function control registers. When this pin is low, all program addresses will access external program memory. These are voltage pins. All VDD pins (9, 17, 37, 67, 93) should be connected to the supply voltage (for MSM66585 connect pins 9, 10, 17, 37, 67, 93). These are ground pins. All GND pins (16, 40, 68, 94) should be connected to ground (for MSM66585 connect pins 11, 16, 40, 68, 94).
P9_0P9_3/ A16-A19 P9_4-P9_7
I/O
P10_0-P10_7
I/O
P12_0-P12_1 P12_2-P12_3/ INT2-INT3 P12_4-P12_7
I/O
AI0-AI3 VREF AGND OSC0 OSC1 NMI RES
I I I I O I I
EA
I
VDD GND
I I
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Semiconductor
MSM66585/586/587/P587/Q587
MEMORY MAP
Program Area
Segment 0 0000H Vector table area 74 bytes 0049H 004AH 0069H 006AH 0071H 0072H 0FFFH 1000H ACAL area 2 KB 17FFH 1800H VCAL table area 32 bytes Vector table area 8 bytes 0000H Segment 1 to 15
Internal ROM area
External ROM area
0FFFH 1000H 17FFH 1800H
ACAL area 2 KB
FFFFH
FFFFH
* For M66585 and M66586 addresses 0C000H to 0FFFFH of segment 0 are external ROM area.
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Data Area
Segment 0 Segment 1-15 SFR area Expanded SFR area Common area FIX area
BCB Common range 0 0-03FFH 1 0-1FFFH 2 0-3FFFH 3 0-7FFFH
0000H
Semiconductor
SFR area
0000H
Expanded SFR area
00FFH 0100H 01FFH 0200H 02FFH 0300H 03FFH
FIX area
Internal RAM area
Local register setting area
09FFH 0A00H Fixed page area
01FFH Expanded SFR area 0200H X1 X2 DP SCB=0 USP X1 0208H X2 DP SCB=1 USP X1 0210H
Pointing register sets
0FFFH 1000H 1FFFH 3FFFH 7FFFH ROM window setting area External memory area
0FFFH 1000H
0238H
USP X1 X2 DP USP 0240H
SCB=7
7FFFH 8000H
ROM window setting area
External memory area
02C0H SBA area 64 bytes 0300H The SBA area that can be accessed using SB, RB, JBS, and JBR instruction.
FFFFH
FFFFH
MSM66585/586/587/P587/Q587
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Semiconductor Area For Setting Local Registers
0000H 0100H 0200H Internal RAM area 0300H SFR area Expanded SFR area FIX area
MSM66585/586/587/P587/Q587
0200H Area for setting local registers: Specify 8-byte block with 8-bits of LRBL
ER0 ER1 ER2 ER3 ER0
0A00H 0208H
R0 R1 R2 R3 R4 R5 R6 R7 R0 R1
LRBL= 00H
LRBL= 01H
External RAM area
FFFFFH 0A00H
ER3
R6 R7
LRBL= FFH
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Semiconductor
MSM66585/586/587/P587/Q587
ABSOLUTE MAXIMUM RATINGS
Parameter Digital power supply voltage Input voltage Output voltage Analog power supply voltage Analog reference voltage Analog input voltage Power dissipation Storage temperature Symbol VDD VI VO AVDD VREF VAI PD TSTG Ta=70C Per package Per output -- GND=AGND=0V Ta=25C Conditions Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to AVDD+0.3 -0.3 to VREF 650 8 -50 to +150 Units V V V V V V mW mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Digital power supply voltage Analog reference voltage Analog input voltage Memory hold voltage Operating frequency Temperature range Symbol VDD VREF VAI VDDH fOSC Ta Conditions fOSC20MHz fOSC10MHz -- -- fOSC=0Hz VDD=5V10% VDD=2.7 to 5.5V -- MOS loads P0, P5_4, P5_5, P7_0, P7_1 TTL loads P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12 Range 4.5 to 5.5 2.7 to 5.5 AVDD-0.3 to AVDD AGND to VREF 2.0 to 5.5 2 to 20 2 to 10 -30 to +70 20 2 V V V V MHz MHz C -- -- Units
Fan-out
N
1
--
ALLOWABLE OUTPUT CURRENT
(VDD=2.7 to 5.5V, Ta=-30 to +70C) Parameter "H" output pin (1 pin) "H" output pin (total) "L" output pin (1 pin) Pin All output pins Total of all output pins All output pins Total of P0, P1, P5 and P7 Total of P2, P9 and P10 "L" output pin (total) Total of P4 and P8 Total of P6 and P12 Total of all output pins 100 SIOL -- -- 50 Symbol IOH SIOH IOL Min. -- -- -- Typ. -- -- -- Max. -2 -40 5 mA Units
Note: Power and ground connections must be made to all external VDD and GND pins. 11/24
Semiconductor
MSM66585/586/587/P587/Q587
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD=5V10%)
(Ta=-30 to +70C) Parameter Input high voltage Input low voltage Input low voltage Output high voltage Output high voltage Output low voltage Output low voltage Input leakage current Input current Input current 1 1 2, 4, 5, 6, 7 1, 4 2 1, 4 2 3, 6 5 7 ILO Rpull CI CO IREF IDDS IDDH IDD VO=VDD/0V VI=0V f=1MHz, Ta=25C A/D conversion operating A/D conversion stopped VDD=2V, Ta=25C* * fOSC=20MHz, No Load IIH/IIL VI=VDD/0V VOL VOH Input high voltage 2, 4, 5, 6, 7 Symbol VIH VIL Conditions -- -- IO=-400mA IO=-2.0 mA IO=-200mA IO=-2.0 mA IO=3.2mA IO=5.0mA IO=1.6mA IO=5.0mA Min 0.44VDD 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.6 VDD-0.4 VDD-0.6 -- -- -- -- -- -- -- -- 25 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 5 7 -- -- 0.2 1 10 45 Max VDD+0.3 VDD+0.3 0.16VDD 0.2VDD -- -- -- -- 0.4 0.8 0.4 0.8 1/-1 1/-250 15/-15 10 100 -- -- 4 10 10 100 25 70 mA kW pF mA mA mA mA mA V Units
Output leakage current 1, 2, 4 2 Pull-up resistor Input capacitance Output capacitance Analog reference power supply current Supply current (stop mode) Supply Current (halt mode) Supply Current
1. 2. 3. 4. 5. 6. 7. *
Applies to P0. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12. Applies to Ain. Applies to P5_4, P5_5, P7_0, P7_1. Applies to RES. Applies to EA, NMI. Applies to OSC0. For input ports, VDD or 0 V. For other cases, unloaded.
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Semiconductor DC Characteristics (2.7V VDD 5.5V)
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Input high voltage Input low voltage Input low voltage Output high voltage Output high voltage Output low voltage Output low voltage Input leakage current Input current Input current 1 1 2, 4, 5, 6, 7 1, 4 VOH 2 1, 4 VOL 2 3, 6 5 7 ILO Rpull CI CO VO=VDD/0V VI=0V,VDD=5V10% VI=0V, VDD=3V10% f=1MHz, Ta=25C A/D conversion operating A/D conversion stopped IDDS IDDH IDD * VDD=5V10% fOSC=10MHz, No Load VDD=3V10% VDD=5V10% VDD=3V10% VDD=5.5V VDD=3.3V VDD=5.5V VDD=3.3V IIH/IIL VI=VDD/0V Input high voltage 2, 4, 5, 6, 7 Symbol VIH VIL Conditions -- -- IO=-400mA IO=-2.0 mA IO=-200mA IO=-2.0 mA IO=3.2mA IO=5.0mA IO=1.6mA IO=5.0mA Min 0.44VDD 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.6 VDD-0.4 VDD-0.8 -- -- -- -- -- -- -- -- 25 40 -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 100 5 7 -- -- -- -- 0.2 1 5 3 30 13 Max VDD+0.3 VDD+0.3 0.16VDD 0.2VDD -- -- -- -- 0.5 0.9 0.5 1.2 1/-1 1/-250 15/-15 10 100 200 -- -- 4 2 10 5 10 100 15 10 50 25 mA mA mA kW pF mA mA mA V Units
Output leakage current 1, 2, 4 Pull-up resistor Input capacitance Output capacitance Analog reference power supply current
IREF
Supply current (stop mode) Supply current (halt mode) Supply current
VDD=2V, Ta=25C*
1. 2. 3. 4. 5. 6. 7. *
Applies to P0. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12. Applies to Ain. Applies to P5_4, P5_5, P7_0, P7_1. Applies to RES. Applies to EA, NMI. Applies to OSC0. For input ports, VDD or 0 V. For other cases, unloaded.
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Semiconductor AC Characteristics (VDD=5V10%) * External Program Memory Control
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Clock (OSC) pulse width ALE pulse width PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time High address hold time Instruction setup time Instruction hold time Symbol tfW tAW tPW tPAD tALS tALH tAHS tAPH tIS tIH CL=50pF Conditions -- Min 25 2tfW-2 2tfW-5 tfW-3 2tfW-3 tfW-3 4tfW-3 0 15 0 Max -- -- -- tfW+3 2tfW+3 tfW+3 4tfW+3 tfW+3 -- tfW-3 ns Units
CLK tfW ALE tAW PSEN tPAD AD 0-AD7 PC 0-7 tALS A 8-A19 tAHS tALH PC 8-19 tAPH tPW INST 0-7 tIS tIH tfW
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Semiconductor * External Data Memory Control
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Clock (OSC) pulse width ALE pulse width RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time Low address hold time High address setup time High address hold time Memory data setup time Memory data hold time Data delay time Data hold time Symbol tfW tAW tRW tWW tRAD tWAD tALS tALH tAHS tAHH tMS tMH tDD tDH CL=50pF Conditions -- Min 25 2tfW-2 2tfW-5 2tfW-5 tfW-3 tfW-3 2tfW-3 tfW-3 3tfW-3 tfW-3 15 0 tALH-0 tfW-3 Max -- -- -- -- tfW+3 tfW+3 2tfW+3 tfW+3 3tfW+3 tfW+3 -- tfW-3 tALH+5 tfW+3 ns Units
CLK tfW ALE tAW RD tRAD AD 0-AD7 RAP 0-7 tALS A 8-A19 tAHS WR tWAD AD 0-AD7 RAP 0-7 tALS tALH tDD RAP 8-19 tAHS tAHH tWW DOUT 0-7 tDH tALH RAP 8-19 tAHH tRW DIN 0-7 tMS tMH tfW
A 8-A19
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Semiconductor * Serial Port Contorl Master mode
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Clock (OSC) pulse width Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tfW tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL=50pF Conditions -- Min. 25 8tfW 4tfW-5 3tfW-10 20 0 Typ. -- -- -- -- -- -- Max. -- -- -- -- -- -- ns Units
SCK tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS
Valid
tSTMXS
Valid
tSRMXH
16/24
Semiconductor Slave mode
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Clock (OSC) pulse width Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tfW tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL=50pF Conditions -- Min. 25 8tfW 2tfW-15 4tfW-10 20 0 Typ. -- -- -- -- -- -- Max. -- -- -- -- -- -- ns Units
SCK tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS
Valid
tSTMXS
Valid
tSRMXH
AC timing mesurement point
VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0V
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Semiconductor AC Characteristics (2.7V VDD 5.5V) * External Program Memory Control
MSM66585/586/587/P587/Q587
(Ta= -30 to +70C) Parameter Clock (OSC) pulse width ALE pulse width PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time High address hold time Instruction setup time Instruction hold time Symbol tfW tAW tPW tPAD tALS tALH tAHS tAPH tIS tIH CL=50pF Conditions -- Min 50 2tfW-4 2tfW-10 tfW-6 2tfW-6 tfW-6 4tfW-6 0 30 0 Max -- -- -- tfW+6 2tfW+6 tfW+6 4tfW+6 tfW+6 -- tfW-6 ns Units
CLK tfW ALE tAW PSEN tPAD AD 0-AD7 PC 0-7 tALS A 8-A19 tAHS tALH PC 8-19 tAPH tPW INST 0-7 tIS tIH tfW
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Semiconductor * External Data Memory Control
MSM66585/586/587/P587/Q587
(Ta= -30 to +70C) Parameter Clock (OSC) pulse width ALE pulse width RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time Low address hold time High address setup time High address hold time Memory data setup time Memory data hold time Data delay time Data hold time Symbol tfW tAW tRW tWW tRAD tWAD tALS tALH tAHS tAHH tMS tMH tDD tDH CL=50pF Conditions -- Min 50 2tfW-4 2tfW-10 2tfW-10 tfW-6 tfW-6 2tfW-6 tfW-6 3tfW-6 tfW-6 30 0 tALH-0 tfW-6 Max -- -- -- -- tfW+6 tfW+6 2tfW+6 tfW+6 3tfW+6 tfW+6 -- tfW-6 tALH+10 tfW+6 ns Units
CLK tfW ALE tAW RD tRAD AD 0-AD7 RAP 0-7 tALS A 8-A19 tAHS WR tWAD AD 0-AD7 RAP 0-7 tALS tALH tDD RAP 8-19 tAHS tAHH tWW DOUT 0-7 tDH tALH RAP 8-19 tAHH tRW DIN 0-7 tMS tMH tfW
A 8-A19
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Semiconductor * Serial Port Control Master mode
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C) Parameter Clock (OSC) pulse width Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tfW tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL=50pF Conditions -- Min. 50 8tfW 4tfW-10 3tfW-20 30 0 Typ. -- -- -- -- -- -- Max. -- -- -- -- -- -- ns Units
SCK tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS
Valid
tSTMXS
Valid
tSRMXH
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Semiconductor Slave mode
MSM66585/586/587/P587/Q587
(Ta= -30 to +70C) Parameter Clock (OSC) pulse width Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tfW tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL=50pF Conditions -- Min. 50 8tfW 2tfW-30 4tfW-20 30 10 Typ. -- -- -- -- -- -- Max. -- -- -- -- -- -- ns Units
SCK tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS
Valid
tSTMXS
Valid
tSRMXH
AC timing mesurement point
VDD
0.8VDD 0.2VDD
0.8VDD 0.2VDD
0V
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Semiconductor A/D Converter Characteristics
MSM66585/586/587/P587/Q587
(Ta=-30 to +70C, VDD=VREF=5V10%, AGND=GND=0V, fOSC=20MHz) Item Resolution Linearity error Differential linearity error Zero scale error Full scale error Conversion time Symbol n EL ED EZS EFS tCONV Conditions
Refer to the recommended circuit Analog input source impedance
Min -- -- -- -- -- 6.4
Typ 8 -- -- -- -- --
Max -- 2 1 +2 -2 19.2
Units Bit
RI5kW tCONV=19.2msec by ADTM set data
LSB
ms/CH
A/D Converter Characteristics
(Ta=-30 to +70C, VDD=VREF=3V10%, AGND=GND=0V, fOSC=10MHz) Item Resolution Linearity error Differential linearity error Zero scale error Full scale error Conversion time Symbol n EL ED EZS EFS Conditions
Refer to the recommended circuit Analog input source impedance
Min -- -- -- -- -- --
Typ 8 -- -- -- -- 38.4
Max -- 1 0.5 +1 -1 --
Units Bit
RI5kW tCONV=38.4msec
LSB
tCONV ADTM=00b (384CLK selection)
ms/CH
Reference Voltage
VREF 0.1 mF
- +
VDD + 0.1 mF 47 mF
+5V
47 mF
+
RI AI0~ AI3 AGND CI GND 0.1 mF
Analog Voltage
0V
RI (analog input source impedance) 5kW Cl = 0.1 mF
Recommended Circuit
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Semiconductor Definition of terms * Resolution
MSM66585/586/587/P587/Q587
Resolution is the minimum input analog value that can be resolved. With 8 bits, 28=256 so resolution can be to (VREF-AGND) / 256. * Linearity error Linearity error is the difference between actual conversion characteristics and ideal conversion characteristics of an 8-bit A/D converter (so this does not include quantization error). Ideal conversion characteristics would be to divide the voltage between VREF and AGND into 256 equal steps. * Differential linearity error Differential linearity error indicates slope of conversion characteristics. The change in analog input voltage value that would change the digital output by one bit is ideally 1 LSB = (VREF-AGND) / 256, so differential linearity error is the difference between this ideal bit size and the actual bit size anywhere in the conversion range. * Zero scale error Zero scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from 00H to 01H. * Full scale error Full scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from FEH to FFH.
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Semiconductor
MSM66585/586/587/P587/Q587
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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